PCF8583 CLOCK CHIP
The only Forth words you are likely to need are W@ and W! . These read the date & time from, and write to, the PCF8583 clock chip. See TIMEKEEPING, page 93 for more information. However more advanced applications may need direct access to clock chip registers and this chapter gives details of their layout.
Although the clock and alarm registers occupy only the area hex 00 to 0F you should be aware that the system needs location hex 10 to store the year number (years starting 1984). You have hex 11 to FF available as non-volatile RAM for applications use.
This description is limited to the 32,768Hz clock mode used on the TDS2020F by the PCF8583 chip. Much of the information here comes from the Philips data sheet on the device and you are advised to consult the original for any further details needed.
PCF8583 block diagram
COUNTER FUNCTION MODES
The hundredths of a second, seconds, minutes, hours, date, month (four-year calendar) and weekdays are stored in a BCD format. The timer register stores up to 99 days.
When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore faulty reading of the count during a carry condition is prevented.
ALARM FUNCTION MODES
By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated.
By setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm may be programmed. The timer register (address 07) may be programmed to count hundredths of a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open drain interrupt output is switched on (active LOW, connected to TDS2020F NMI pin) when the alarm or timer flag is set (enabled).
When a timer function without any alarm function is programmed the remaining alarm registers (addresses 09 to 0F) may be used as free RAM space.
The control/status register is memory location 00 and can be written and read via the I2C bus. All functions and options are controlled by the contents of this register, its default value on the TDS2020F is hex 00.
It is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states will lead to a clock malfunction but will not latch-up the device.
The three diagrams show more details of the layout of the registers at addresses 04 to 06. 24 or 12 hour format can be selected by setting the most significant bit of the hours counter register, address 04.
The year and date are packed into address 05, the weekdays and month into address 06. When reading these locations the year and weekdays are masked out when the mask flag of the control/status register is set. This allows you to read the date and month count directly.
Hours, year/date and weekdays/months counters
ALARM CONTROL REGISTER
When the alarm enable bit of the control/status register is set the alarm control register (address 08) is activated. All alarm, timer and interrupt output functions are controlled by the contents of the alarm control register.
Alarm control register
All alarm registers are allocated with a constant address offset of 08 to the corresponding counter registers.
An alarm goes off when the content of the alarm registers matches bit-by-bit the content of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated.
Selection of alarm weekdays
Setting the alarm control register programs the open drain n-channel interrupt output. It is switched on (active LOW) when the alarm flag or the timer flag is set. Without alarm the timer flag controls the output sequence.
On TDS2020F the interrupt is connected to the processor's NMI and there is an on-board 100k pull-up resistor. If you are adding more sources of Non-Masked Interrupt or have a long NMI lead connected which add extra capacitance the NMI may rise too slowly, causing multiple interrupts. Since there is no Schmitt trigger on the NMI input you might need one externally or an extra pull-up-start with 10k.
A trimmer capacitor is provided on TDS2020F for fine adjustment of the 32,768Hz frequency at which the clock chip operates. It is not set at manufacture and allows the clock to give timekeeping of the order of 1 minute per month.